1. Field of the Invention
The present invention relates to a differential amplifier circuit, and more specifically, to a rail to rail input/output differential amplifier circuit.
2. Description of the Related Art
A conventional differential amplifier circuit is described. FIG. 3 is a circuit diagram illustrating the conventional differential amplifier circuit.
The conventional rail to rail input/output differential amplifier circuit includes a first input stage formed of a PMOS transistor 61 and PMOS transistors 65 and 66, a second input stage formed of an NMOS transistor 71 and NMOS transistors 75 and 76, and a folded cascode amplifying stage formed of PMOS transistors 62 and 63 and NMOS transistors 72 and 73 (see, for example, Japanese Patent Application Laid-open No. 2005-223627 (FIG. 9)). The conventional differential amplifier circuit further includes an output stage formed of a PMOS transistor 64 and an NMOS transistor 74 so as to have a wide output voltage range.
Drain currents of the PMOS transistors 61 to 66 are drain currents I61 to I66, respectively. Drain currents of the NMOS transistors 71 to 76 are drain currents I71 to I76, respectively. An input voltage at an input terminal inp is Vinp, and an input voltage at an input terminal inn is Vinn. Here, the drain currents I62 and I63 are defined as a current 2I, and a current flowing into a drain of the NMOS transistor 73 is defined as a current IB.
The differential amplifier circuit having the above-mentioned configuration operates as follows.
If the input voltage Vinp becomes higher than the input voltage Vinn, the drain current I65 becomes smaller than the drain current I66, and the drain current I75 becomes larger than the drain current I76. The current IB (IB=2I−I75+I65) becomes smaller than the drain current I73 (I73=I72=2I−I76+I66), and hence a gate voltage of the NMOS transistor 74 is reduced. Therefore, an ON-state resistance of the NMOS transistor 74 is increased to increase an output voltage Vout.
On this occasion, when the input voltage Vinp and the input voltage Vinn are close to VDD, the PMOS transistor 61 operates in the non-saturation region, and the differential amplifier circuit operates with the NMOS transistors 75 and 76 serving as inputs. On the other hand, when the input voltage Vinp and the input voltage Vinn are close to VSS, the NMOS transistor 71 operates in the non-saturation region, and the differential amplifier circuit operates with the PMOS transistors 65 and 66 serving as inputs. Further, when the input voltage Vinp and the input voltage Vinn are intermediate voltages, the differential amplifier circuit operates with both of the NMOS transistors 75 and 76 and the PMOS transistors 65 and 66 serving as the inputs.
Through the above-mentioned operations, the conventional differential amplifier circuit can perform rail to rail input/output.
However, in the conventional differential amplifier circuit described above, when the input voltage Vinp and the input voltage Vinn are close to VDD or VSS, the currents flowing into the drains of the NMOS transistors 72 and 73 vary, but the current flowing into the drain of the NMOS transistor 74 is constant. Therefore, if the input voltage levels to the differential pair are different, the bias condition is different between the NMOS transistors 72 and 73 and the NMOS transistor 74. In other words, the conventional differential amplifier circuit suffers from a problem that an offset voltage is changed if the input voltage levels to the differential pair are different.